The present invention is directed to the hardening of integrated circuits against single event upsets. These hardened integrated circuits, for example, may be used for data storage.
Integrated circuits are frequently used in the presence of radiation. Radiation, which can be in the form of x-rays, gamma-rays, photons, or particles, deposit charge in silicon and, therefore, can cause upsets in the integrated circuits. The most common upset causes are from such particles as protons, neutrons, and heavy ions. As a result of such radiation, charges can be collected at circuit nodes that send the nodes to opposite voltage states (e.g., from high to low). When this voltage state change happens to a data storage circuit, the data storage nodes change to the opposite data states. All circuits can tolerate some amount of deposited charge that does not cause a data state change. However, all circuits also have some deposited charge threshold above which the data state will be changed. This threshold is referred to as the critical charge (i.e., Qcrit) for upset. Such data state changes are defined as radiation induced upsets. When radiation particles, which are particles that are discrete in time and space, cause a data upset, the data upset is referred to as a single event upset (SEU).
For a circuit node to collect charge, a particle must penetrate the silicon region coupled to that node, and the particle must also pass through, or be close to, a voltage gradient. Charge is only collected from silicon regions where the time that the charge drifts or diffuses into a voltage gradient is greater than the recombination time. An shown in FIG. 1, a portion of an integrated circuit 10 includes a reverse biased pn junction 12 such as found on the drain of an off n-channel transistor (an n-channel transistor in an off state) that is being driven high by a p-channel transistor.
As shown in FIG. 1, a particle passes along track #1 through the n-channel drain pn junction and depletion region. As a result, hole-electron pairs are generated along the entire length of track #1. The number of such generated hole-electron pairs is dependent on the mass and energy of the particle.
In the N+ region shown in FIG. 1, the concentration of impurities is typically so high that lifetimes are very short. Therefore, the generated hole-electron pairs in the N+ region recombine before they can move.
In the depletion region, however, there is an electric field that quickly separates the holes and electrons, sending the holes to the Pxe2x88x92 region and the electrons to the N+ region before they can recombine. Charge that moves under the influence of an electric field is known as drift current. The holes and electrons are majority carriers in these regions and, therefore, create a current that discharges the V+ node and charges the ground node.
In the Pxe2x88x92 region, lifetimes are much longer than in the N+ region. Therefore, there is time for the holes and electrons to diffuse away from the particle track. The movement of charge from regions of high concentration to regions with lower charge concentration is known as diffusion current. Some holes and electrons diffuse toward the depletion region. The electrons diffusing toward the depletion region accelerate across and into the N+ region. However, the holes diffusing toward the depletion region are thrown back into the Pxe2x88x92 region.
Accordingly, the particle moving along track #1 creates a sudden discharge current on the V+ node. If the amount of collected charge is large enough to overcome the capacitance and V+ drive at this portion of the integrated circuit 10 (i.e., the p-channel transistor does not have sufficient drive to prevent the V+ node from discharging to ground), and if this node is part of a feedback path, then the particle moving along track #1 could result in a change of (i.e., an error in) the stored data state. If the data state does change, this change is known as a SEU (single event upset).
Likewise, a reverse biased pn junction such as found on the drain of an off p-channel transistor being driven by an n-channel transistor can experience a similar charging current from a particle passing through it.
The time that it takes the radiation particle to traverse the depletion region and generate the hole-electron pairs is on the order of a picosecond, which is much shorter than typical system operating frequencies. The time that it takes the charge to traverse the depletion region is also on the order of picoseconds. Lifetimes in the Pxe2x88x92 region are much longer. Thus, the nature of the current produced by a radiation particle traversing a reverse biased pn junction begins as a large current pulse of short duration (the charge deposited in the depletion region traversing this depletion region, i.e., drift current). This pulse is followed by a much smaller current of longer duration (the charge deposited outside the depletion region diffusing to the depletion region, i.e., diffusion current, and then traversing the depletion region). Generally, it is the initial large current pulse to which a data storage circuit is most vulnerable. Thus the stored data state disturbing current produced by a radiation particle is a transient phenomena that occurs in a time much smaller than operating frequencies.
Because the data state of a node upset by a radiation particle passing through it can be restored by rewriting the original stored data state, the change in state of the upset node is known as a soft error. There is a time and spatial distribution of particles that have a range of mass and energy. An upset can only be predicted in terms of the probability (i.e., rate) of a particle with sufficient mass and energy to traverse a depletion region with a sufficiently long track length of deposited charge that exceeds Qcrit. The rate at which these soft errors occur is known as the soft error rate (SER). The SER is proportional to the volume of the sensitive region and is inversely proportional to Qcrit.
If the N+ region in FIG. 1 is at ground instead of at V+ as shown, there is no reverse biased depletion region. Instead, there is only the space charge region typically associated with the built-in pn junction potential of 0.7V. At least in some respects, the behavior of the node with a grounded N+ region is similar to the reverse biased conditions described above. That is, when a particle passes through the space charge region of this node whose N+ region is grounded, the deposited charge discharges the N+ node. However, when the grounded N+ region discharges to xe2x88x920.7V, the pn junction becomes forward biased, and holes consequently sweep into the N+ region to recombine with the electrons that were initially swept into the N+ region.
Thus, the maximum voltage change for the N+ region of this node is xe2x88x920.7V, which actually is a harder low state on the node. Accordingly, a radiation particle passing along track #1 of FIG. 1, where the N+ region is grounded, cannot create an SEU. Likewise, a P+/Nxe2x88x92 junction where both sides are high at VDD will only go to VDD +0.7V when a particle strikes the space charge region.
Therefore, as can be seen, there must be a reverse biased condition in order for an SEU to occur.
A radiation particle moving along track #2 shown in FIG. 1 also creates hole-electron pairs along the track, and these hole-electron pairs can diffuse into the depletion region. However, the diffusion process is much slower than the drift process corresponding to particle track #1. Therefore, a smaller current corresponding to particle track #2 is created compared to the current corresponding to particle track #1. Therefore, SEUs are created primarily by particles passing through the depletion region. As a result, the depletion region defines the sensitive volume for an SEU. (The sensitive volume for charge collection is the region from which a node collects charge.)
In bulk silicon technology, the depletion region of a node is principally the region under the drain. Therefore, the sensitive volume is also principally the region under the drain. There also are depletion regions surrounding the drain and under the gate, but these regions are generally small compared to the region under the drain. Therefore, the sensitive volume in bulk silicon technology is the drain region.
In SOI (Silicon On Insulator) technology, there is no depletion region under the drain. There is a depletion region under the gate, and there may or may not be a depletion region around the remaining sides of the drain. Therefore, the sensitive volume in SOI technology is generally the gate region, but may also include some additional perimeter of the drain.
FIG. 2 shows an off SOI n-channel transistor 14 with a particle track #1 passing through a depletion region 16 under the gate of the SOI n-channel transistor 14 and a particle track #2 passing through a drain perimeter depletion region 18 extending out from the non-gate perimeter of the drain of the SOI n-channel transistor 14. Both of these tracks introduce charge to the V+ node in the same manner as described above.
In addition, SOI devices are especially vulnerable to an additional current flow mechanism that can be triggered by a particle. This additional flow mechanism can be understood with reference to FIG. 2. Particle track #1 shown in FIG. 2 passes through the silicon region under the gate (i.e., transistor substrate node) of the SOI n-channel transistor 14. The depletion region 16 moves electrons to the drain N+ region and holes oppositely into the Pxe2x88x92 region under the gate. The V+ node collects the electrons, but the holes continue to collect in the Pxe2x88x92 region under the gate. This hole collection raises the Pxe2x88x92 voltage until a pn junction forward bias occurs with the source region.
Moreover, the MOSFET source/substrate/drain structure is also a parasitic NPN bipolar structure, where the source is the emitter of the bipolar structure, where the substrate is the base of the bipolar structure, where the drain is the collector of the bipolar structure, and where the base/emitter junction is forward biased by the collection of charge as described above. This forward biasing creates a collector current that is equal to the base current (which is created by the charge deposited by a particle strike) times the gain of the parasitic bipolar transistor (parasitic BJT). Accordingly, the drain current is greater than can be directly attributed to the hole-electron pairs generated by the particle.
This additional current flow must be avoided in order to avoid an upset. Therefore, it is important to sweep the accumulating holes in the Pxe2x88x92 region out directly to the ground node as shown in FIG. 3. However, even in this case, there is a resistance associated with the Pxe2x88x92 region such that the resulting IR drop could still result in a forward bias of the substrate/source junction.
FIG. 3 is a top view of the transistor shown in FIG. 2. As shown in FIG. 3, the Pxe2x88x92 substrate is coupled directly to ground. Arrows show the resulting hole-electron movement. However, there is resistance in the Pxe2x88x92 substrate region through which the holes move that will create an IR drop. This resistance must be kept low enough to prevent the IR drop from forward biasing the substrate/source junction.
SEU hardening of integrated circuits have been implemented to prevent single event upsets. Generally, two methods have been used to implement SEU hardening of data storage circuits (i.e. memory cells, latches, flip-flops, registers, etc.). In the first method, logic is added to the integrated circuit. However, this first method has significantly increased area, delay, and power. In the second method, RC delay (usually involving one or two resistors whose resistance is in the neighborhood of 10,000 ohms to more than 100,000 ohms) has been added to the feedback path in the integrated circuit. However, the second method places a large RC delay in the write path of the integrated circuit, thereby increasing delay. The second method also requires additional processing for the dedicated resistive element(s).
The present invention achieves SEU hardening without additional processing, without significantly increasing delay and power, and without increasing sensitivity to SEUs.
In accordance with one aspect of the present invention, a hardening system comprises a data storage device and a hardening circuit. The data storage device has a data input, a clock input, and a data state reinforcing feedback path having a data node Q and a data complement node QN, and the data storage device provides drive to the data node Q and the data complement node QN. The hardening circuit is coupled to the data state reinforcing feedback path, and the hardening circuit provides extra drive to the data node Q and the data complement node QN so as to prevent the data node Q and the data complement node QN from changing states in the presence of radiation. The hardening circuit provides full rail drive to internal nodes of the hardening circuit.
In accordance with another aspect of the present invention, a hardening circuit for an integrated circuit having a data state reinforcing feedback path with a data node Q and a data complement node QN comprises first and second hardening transistors and first and second gate control circuits. The first hardening transistor is coupled between a rail and the data node Q, and the first hardening transistor is arranged to provide additional drive to the data node Q. The second hardening transistor is coupled between the rail and the data complement node QN, and the second hardening transistor is arranged to provide additional drive to the data complement node QN. The first gate control circuit is coupled between a clock input and a gate of the first hardening transistor, the first gate control circuit includes first and second transistor paths each having a control input, the control input of the first transistor path is coupled to the data node Q, and the control input of the second transistor path is coupled to the data complement node QN. The second gate control circuit is coupled between the clock input and a gate of the second hardening transistor, the second gate control circuit includes third and fourth transistor paths each having a control input, the control input of the third transistor path is coupled to the data complement node QN, and the control input of the fourth transistor path is coupled to the data node Q. The first and second gate control circuits provide full rail drive to internal nodes of the hardening circuit.
In accordance with still another aspect of the present invention, a hardening system comprises a positive-level-sensitive D latch, first and second p-channel hardening transistors, and first and second gate control circuits. The positive-level-sensitive D latch has a data input, a clock input, and a data state reinforcing feedback path having a data node Q and a data complement node QN, and the positive-level-sensitive D latch is coupled between rails VDD and VSS. The first p-channel hardening transistor is coupled between the rail VDD and the data node Q, and the first p-channel hardening transistor provides drive to the data node Q in addition to drive provided by the positive-level-sensitive D latch. The second p-channel hardening transistor is coupled between the rail VDD and the data complement node QN, and the second p-channel hardening transistor is arranged to provide drive to the data complement node QN in addition to drive provided by the positive-level-sensitive D latch. The first gate control circuit is coupled between the clock input and a gate of the first p-channel hardening transistor, the first gate control circuit includes a first n-channel transistor path and a first p-channel transistor path each having a control input, the control input of the first n-channel transistor path is coupled to the data node Q, and the control input of the first p-channel transistor path is coupled to the data complement node QN. The second gate control circuit is coupled between the clock input and a gate of the second p-channel hardening transistor, the second gate control circuit includes a second n-channel transistor path and a second p-channel transistor path each having a control input, the control input of the second p-channel transistor path is coupled to the data node Q, and the control input of the second n-channel transistor path is coupled to the data complement node QN. The first and second gate control circuits provide full rail drive to the internal nodes of the hardening system.
In accordance with yet another aspect of the present invention, a hardening system comprises a negative-level-sensitive D latch, first and second n-channel hardening transistors, and first and second gate control circuits. The negative-level-sensitive D latch has a data input, a clock input, and a data state reinforcing feedback path having a data node Q and a data complement node QN, and the negative-level-sensitive D latch is coupled between rails VDD and VSS. The first n-channel hardening transistor is coupled between the rail VDD and the data node Q, and the first n-channel hardening transistor is arranged to provide drive to the data node Q in addition to drive provided by the negative-level-sensitive D latch. The second n-channel hardening transistor is coupled between the rail VDD and the data complement node QN, and the second n-channel hardening transistor is arranged to provide drive to the data complement node QN in addition to drive provided by the negative-level-sensitive D latch. The first gate control circuit is coupled between the clock input and a gate of the first n-channel hardening transistor, the first gate control circuit includes a first n-channel transistor path and a first p-channel transistor path each having a control input, the control input of the first n-channel transistor path is coupled to the data complement node QN, and the control input of the first p-channel transistor path is coupled to the data node Q. The second gate control circuit is coupled between the clock input and a gate of the second n-channel hardening transistor, the second gate control circuit includes a second n-channel transistor path and a second p-channel transistor path each having a control input, the control input of the second p-channel transistor path is coupled to the data complement node QN, and the control input of the second n-channel transistor path is coupled to the data node Q. The first and second gate control circuits provide full rail drive to the internal nodes of the hardening system.